Futurebus+ is an IEEE specification for high-performance backplane-based computing that permits architectural consistency across a broad range of computer products. Key attributes of Futurebus+ are discussed in the article of J. Theus in Microprocessor Report, Volume 6, Number 7, May 27, 1992. Futurebus+ is a comprehensive architectural specification designed as an open standard; that is, an interface standard for which there are no preconceived restrictions in terms of architecture, microprocessor, and software implementations. It is also a standard explicitly designed to support multiple generations of computer technology, leading to system speeds significantly greater than current systems.
Futurebus+ provides a 64-bit architecture with a compatible 32-bit subset and data path extensions to 128 or 256 bits. The protocols, while providing headroom for system growth, explicitly support real-time scheduling, fault tolerance, and high-availability and high-reliability systems.
The logical layering of the Futurebus+ specifications offers a wealth of architectural features with which designers may implement a wide variety of systems. Both loosely coupled and tightly coupled compute paradigms are supported via the parallel protocols and in the message-passing and cache-coherence protocols. The control and status registers provide a standard software interface to the Futurebus+, easing the development and transportability of I/O drivers and other system software.
Unlike older standard buses, Futurebus+ is optimized for a backplane environment. Backplane transceiver logic (BTL) circuits provide incident-wave switching capability (thus no set-up and hold time), low capacitance with high current drive capability, and controlled one-volt voltage swings for better noise margins.
While the present invention can be used in conjunction with Futurebus+ , a few aspects of the present invention are: buffering between multiple transfer types, transferring data between multiple time domains, and buffering data between different size busses. The resolution of the problems associated with these issues is the basis of the instant invention.
Three modes of transferring information have evolved over the past several years: high speed packet transfers, asynchronous compelled transfers, and synchronous transfers. Interfacing to all three protocols can lead to architectural and performance problems in the buffering agent.
Packet transfers involve sending a stream of data from one agent to another at a clock rate. At each dock edge, data is captured. The dock can be embedded in the data stream, sent on a separate wire from the source, or be a common frequency between each agent where the receiving agent extracts phase information from start and stop bits, like UARTs. The main limiting factors in packet transfers are the signal integrity (electrical characteristics and electrical environment), bit to bit parallel skew, and serial bit jitter/symetry.
Futurebus has excellent signal integrity; bit to bit parallel skew is avoided by locking onto the phase of the data stream using a pre-determined clock rate; and serial bit jitter/symmetry is tightly controlled in the transceiver. These factors result in a very high-speed packet transfer mechanism, twice as fast as existing CMOS fifo's. An object of the present invention is to provide an architecture that can operate with fifo's which operate at only half the speed of the Futurebus packet transfer.
Compelled asynchronous transfers use a handshaking protocol to transfer data. In a compelled handshake the source supplies data and an indication that data is ready; and the destination receives the data and indicates that data has been received allowing the source to continue with the next operation. A three wire handshake is used on Futurebus+ to transmit data in a compelled way allowing multiple sources and/or destinations. The handshake allows multiple slaves to send data (broadcall) or receive data (broadcast) from the master.
Interfacing between this protocol and a fifo requires asynchronous control. Another object of the present invention is to provide an architecture in which the fifo can operate in both compelled and packet modes.
Synchronous transfers can include single or burst data transfers. Burst data transfers resemble packet transfers where a clock is sent along with the data, except that the entire bus, master and slaves, are all operating at the same speed.
A time domain is a group of circuitry which utilizes a single clock and phase or a common asynchronous protocol. A time domain boundary is the place where two time domains meet. Data crossing a time domain boundary may become corrupted if care is not taken in design of the time domain boundary buffers.
There are two primary mechanisms for data buffering across a time domain boundary: First-In-First-Out (FIFO) buffering configuration and dual-ported random access memory (RAM) with locked control. An aspect of the present invention is combining the features of a dual-ported RAM with the simplicity of FIFO accessing. This allows versatile addressing of accesses while avoiding locking mechanisms.
The FIFO consists of a memory that is accessible by the source of data anytime there is space available; it is available to the destination anytime there is data available from the source. This is the usual way to interface between two time domains.
Dual-ported RAMs are a more versatile form of time domain boundary buffer. They allow reading data in a different order than it was written in: based upon address rather than write order. Dual-ported RAMs provide two ways, ports, to access a common memory element. Locks are used to prevent reading from a memory element while it is being written.
Finally, the interface must handle bus size buffering. Futurebus+ and the host interface can both be configured to be 32 or 64 bits wide. One bus can be 32 bits wide and the other can be 64 bits wide. This my lead to byte order problems as data is dynamically transferred from one port to the other. This problem is typically avoided by constraining each port to the same size, thereby avoiding dynamic bus sizing problems.